The present invention relates to a testing board for semiconductor memories, method of testing semiconductor memories and a method of manufacturing semiconductor memories and more particularly to technique effective for application to a testing board in which a testing circuit using an ALPG (Algorithmic Memory Pattern Generator) and sockets used to mount semiconductor memories on the testing board as devices to be tested are mounted, a testing method using the testing board and a manufacturing method of semiconductor memories.
Heretofore, a test for semiconductor memories such as RAMs (Random Access Memories) is carried out by a testing apparatus named a memory tester. The memory tester generates a test pattern (address and data) and supplies the semiconductor memories to be tested with the test pattern to be written in memory cells of the semiconductor memories. Then, data written in the memory cells are read out by the memory tester, so that the read-out data are compared with expected values within the memory tester to judge whether the data are identical with the expected values so that the semiconductor memories are diagnosed.
Procedure from manufacture to shipping of semiconductor memories is generally made as shown in FIG. 11. That is, after a plurality of semiconductor memories have been formed on a wafer in a semiconductor manufacturing process, probes come into contact with pads of the semiconductor memories being formed on the wafer to supply test signals thereto and receive output signals in response to the test signals so that the test using the probes is performed (step S11). The semiconductor memories are classified into repairable devices and non-repairable devices on the basis of the test result. With respect to the repairable devices, a redundant circuit provided within each memory is used to replace a defective bit with a spare memory cell (step S12).
Next, the wafer in which the plurality of semiconductor memories are formed is cut into respective chips and each chip is enclosed or sealed by means of resin to be assembled into a package (step S13). The semiconductor memories each assembled into the package are subjected to a high-temperature test (burn-in test) by means of a burn-in apparatus and to a low-speed operation test (long test) by means of a signal such as a clock having a low operation frequency to thereby remove a device having unstable operation on the basis of the test result (steps S14 and S15).
Then, a high-speed memory tester is used to perform a DC test for testing whether the semiconductor memories have a desired DC voltage characteristic by applying a DC voltage to the semiconductor memories, a function test for testing whether circuits are operated normally at usual operation speed with original operation frequency signals, and a timing test for testing whether a set-up time and a hold time of the semiconductor memories satisfy design specification successively (steps S16, S17xe2x80x2 and S18).
The semiconductor memories regarded as non-defective devices are used to assemble a memory module. The memory module is mounted on a mother board of a computer and is subjected to a selection test by means of an actual machine. Only the memory module judged as a normally operated module is shipped as a product (step S19 and S20xe2x80x2).
In the prior art as described above, since the test performed using the memory tester has a lot of test items, there is a problem that the test time is increased and a cost required for the test is increased. In other words, since the number of memories capable of being tested by the memory tester is very small as compared with the burn-in apparatus or the like, the test time is very increased if all of memories are to be tested by means of the limited number of memory testers and since the number of memory testers must be increased if the test is to be completed in a short time, the cost of equipment is very increased.
Further, since the test using the tester is made in accordance with a test pattern having the regularity according to a predetermined algorithm, any defective memory can be sometimes detected even from the memories judged as non-defective devices in the test using the tester if the memories are subjected to the test using a random test pattern. Accordingly, in the conventional test method using the tester, even when the test has been performed using the expensive tester at great pains, it is disadvantageous that the test using the random test pattern must be performed by the actual machine again after the memories have been assembled in a module.
On the other hand, there is proposed an invention that a testing circuit including a test pattern generator named ALPG for generating a memory test pattern in accordance with a predetermined algorithm is mounted in a memory chip to test a memory array by itself so that the frequency in use of the memory tester can be reduced (International Publication WO 98/47152). However, when the ALPG is mounted in the memory chip as in the above invention, it is disadvantageous that the yield is reduced due to a defect of the ALPG itself and the size of the memory chip is increased.
In this connection, the specification of the above invention discloses that the testing circuit having the above-mentioned configuration is structured as a semiconductor integrated circuit separated from the memory chip and the semiconductor integrated circuit and the memory chips are mounted on a board so that the self-test thereof can be realized even in the assembled state in a memory module. However, even the publication of the above invention does not quite disclose the test using a random pattern.
It is an object of the present invention to provide a testing board for semiconductor memories, a testing method and a manufacturing method of the semiconductor memories capable of decreasing the number of testers used in a test and having high speed and high function to reduce the cost of equipment.
It is another object of the present invention to provide a testing board for semiconductor memories, a testing method and a manufacturing method of the semiconductor memories capable of shortening a time required for a test.
It is still another object of the present invention to provide a testing board for semiconductor memories, a testing method and a manufacturing method of the semiconductor memories capable of testing semiconductor memories without reduction in the yield of memory chips and increase in size of the memory chips.
Representatives of the inventions disclosed in the present application are summarized as follows.
According to an aspect of the present invention, a testing circuit using an ALPG is mounted in a testing board in which sockets for mounting semiconductor memories in the board as devices to be tested are mounted and a volatile memory for storing a data table for generating a random pattern is included in the testing board, so that a test using a test pattern having no regularity using the data table is performed in addition to a test using a test pattern having regularity generated by the ALPG.
More particularly, the testing board according to the present invention includes a plurality of sockets in which semiconductor memories to be tested are mounted, a testing circuit for generating addresses and data used for test of the semiconductor memories in accordance with a predetermined algorithm, terminals for connecting the testing circuit to an external control apparatus, and wiring for electrically connecting the sockets, the testing circuit and the terminals, and the testing circuit comprises a volatile memory for storing data forming the basis for generating data used in a test using a test pattern having no regularity, and data generating means for reading out the data from the volatile memory to generate data for the test.
According to the aspect of the present invention described above, since the semiconductor memories can be tested in accordance with the predetermined algorithm by means of the testing circuit on the testing board equipped with the sockets for mounting the semiconductor memories to be tested in the board, a desired test can be performed without using any high-speed and high-function tester and the test using the test pattern having no regularity can be also performed by the testing circuit. Accordingly, the test which is heretofore performed by an actual machine can be performed by a simple and inexpensive testing apparatus such as a burn-in apparatus and further a large number of semiconductor memories can be tested by the testing apparatus at the same time. Moreover, optimum data can be stored in the volatile memory in accordance with contents of the test to perform the test efficiently.
The testing circuit preferably comprises a buffer memory for holding the data generated by the data generating means, and a comparison and judgment circuit for comparing the data stored in the buffer memory with data read from the semiconductor memory mounted in the socket to detect whether both the data are coincident with each other or not. Accordingly, an external control apparatus can obtain a comparison and judgment result from the testing circuit on the board without reading out the data written in the semiconductor memory and making comparison and judgment of the read-out data with respect to expected data.
According to another aspect of the present invention, the testing board includes a plurality of sockets in which semiconductor memories to be tested are mounted, a testing circuit for generating data and addresses used for test of the semiconductor memories in accordance with a predetermined algorithm, a buffer circuit having a buffer memory for holding the data generated by the testing circuit and a comparison and judgment circuit for comparing the data stored in the buffer memory with data read from the semiconductor memory mounted in the socket to detect whether both the data are coincident with each other or not, terminals for connecting the testing circuit to an external control apparatus, and wiring for electrically connecting the sockets, the buffer circuit, the testing circuit and the terminals, and the testing circuit may comprise a volatile memory for storing data forming the basis for generating data used in a test using a test pattern having no regularity, and data generating means for reading out the data from the volatile memory to generate data for the test.
According to the aspects of the present invention described above, since the semiconductor memories can be tested in accordance with the predetermined algorithm by means of the testing circuit on the testing board equipped with the sockets in which the semiconductor memories to be tested are mounted, a desired test can be performed without using any high-speed and high-function tester and the test using the test pattern having no regularity can be also performed by the testing circuit. Accordingly, the test which is heretofore performed by an actual machine can be performed by a simple and inexpensive testing apparatus such as a burn-in apparatus and further a large number of semiconductor memories can be tested by the testing apparatus at the same time. Moreover, an external control apparatus can obtain a comparison and judgment result from the testing circuit on the board without reading out the data written in the semiconductor memory and making comparison and judgment of the read-out data with respect to expected data. In addition, since the testing circuit is not required to be included in the semiconductor memories to be tested, the semiconductor memories can be tested without reducing the yield of memory chips and increasing a chip size.
Furthermore, the testing circuit preferably comprises data indication means for successively generating an address for data to be next read out from the volatile memory. Accordingly, next data can be easily read out from the volatile memory and the order of addresses produced by the data indication means can be changed to thereby enhance the randomness of data read out from the volatile memory.
Further, the testing circuit comprises an address generation unit for generating an address to be supplied to the semiconductor memories mounted in the sockets, a data generation unit for generating data to be supplied to the semiconductor memories mounted in the sockets, and a control unit for controlling the address generation unit and the data generation unit to successively produce a test pattern according to a predetermined algorithm. Accordingly, since the semiconductor memories can be performed in accordance with the predetermined algorithm by means of the testing circuit on the testing board, a desired test can be performed without using any high-speed and high-function tester and a cost required for the test can be reduced. Since a large number of semiconductor memories can be tested at the same time, time required for the test can be shortened.
Moreover, the control unit comprises a memory for storing a program composed of a plurality of control codes, and a program counter for generating an address indicating the control code to be read out from the memory. Accordingly, the control unit capable of controlling the address generation unit and the data generation unit to generate the test pattern in the predetermined algorithm efficiently can be configured.
Further, the memory for storing the program composed of the control codes comprises a volatile memory. Accordingly, each time a test having different contents is performed, the program can be transferred to thereby reduce the capacity of the memory for storing the program and when a more efficient program or a new test is developed, correction and addition with respect to the program and the test can be made easily.
Furthermore, the data generation unit comprises two or more data operation systems each including operation means for performing operation processing to the data read out from the volatile memory and a register for holding an operation result, and data selection means for selecting any of data processed by the data operation systems to be outputted. Accordingly, the test data can be generated at high speed by means of parallel processing of the two data operation systems.
Further, the data operation systems each include a path for feeding back data held in the register to the operation means. Accordingly, since the data once used can be fed back to the operation means and be operated to thereby change the data, more random data can be generated even if the data previously stored in the volatile memory are reduced.
The data indication means includes a memory for holding addresses indicating data to be read out from the volatile memory, and the memory comprises a volatile memory. Accordingly, the order of reading out the data can be changed in accordance with the contents of the test to thereby perform efficient test.
According to another aspect of the present invention, the testing method of semiconductor memories comprises a first test process of testing a plurality of semiconductor memory chips formed on a wafer, a second test process of testing semiconductor memories cut from the wafer and packed into a package under a high temperature, and a third test process of mounting the semiconductor memories subjected to the second test process in a plurality of sockets of a testing board in which the plurality of sockets, a testing circuit for generating addresses and data used for test of the semiconductor memories in accordance with a predetermined algorithm and including a volatile memory for storing data forming the basis for generating data used in a test using a test pattern having no regularity and data generating means for reading out the data from the volatile memory to generate data for the test, terminals for connecting the testing circuit to an external control apparatus, wiring for electrically connecting the sockets, the testing circuit and the terminals are formed, so that the semiconductor memories mounted in the plurality of sockets are tested by the testing circuit.
According to the test method described above, since the semiconductor memories can be tested in accordance with the predetermined algorithm by means of the testing circuit on the testing board including the sockets for mounting the semiconductor memories to be tested, a desired test can be performed without using any high-speed and high-function tester and the test using the test pattern having no regularity can be also performed by the testing circuit. Accordingly, the test which is heretofore performed by an actual machine can be performed by a simple and inexpensive testing apparatus such as a burn-in apparatus and further a large number of semiconductor memories can be tested by the testing apparatus at the same time.
Further, it is preferable that the third test process is performed by the same apparatus as the apparatus used in the second test process. A conventional testing apparatus can be utilized as it is without developing a new testing apparatus to thereby reduce the cost of equipment for test.
According to another aspect of the present invention, a manufacturing method of semiconductor memories comprises a first test process for testing a plurality of semiconductor memory chips formed on a wafer, a process of cutting each of the semiconductor memory chips from the wafer, a process of packing the cut semiconductor memory chip into a package, a second test process of testing semiconductor memories packed into the package under a high temperature; a process of mounting the semiconductor memories subjected to the second test process in a plurality of sockets of a testing board in which the plurality of sockets, a testing circuit for generating addresses and data used for test of the semiconductor memories in accordance with a predetermined algorithm and including a volatile memory for storing data forming the basis for generating data used in a test using a test pattern having no regularity and data generating means for reading out the data from the volatile memory to generate data for the test, terminals for connecting the testing circuit to an external control apparatus, wiring for electrically connecting the sockets, the testing circuit and the terminals are formed, a process of mounting the testing board in a testing apparatus, and a third test process of testing the semiconductor memories by means of the testing apparatus and the testing circuit.
According to the manufacturing method described above, the test which is heretofore performed by an actual machine can be performed by a simple and inexpensive testing apparatus such as a burn-in apparatus and further a large number of semiconductor memories can be also tested at the same time. A manufacturing cost can be reduced greatly and the time required until shipping of product can be shortened greatly.